The present invention involves the field of semiconductor devices and a process of their production. In particular, the invention is directed towards the construction of self-aligned electrically isolated bipolar devices in a semiconductor substrate.
Integrated circuits are generally fabricated as a multiplicity of interconnected devices such as diodes and transistors within a monolithic body of semiconductor material often called a semiconductor wafer. The devices are fabricated side by side within the substrate and must be electrically isolated to prevent the occurrence of any undesired interaction between them. To prevent unwanted interaction, it is common practice to provide some form of electrical isolation barrier between the devices. For example, isolation may be achieved by providing PN junctions between the devices which are readily reverse-biased to preclude current flow across the junction.
While known PN junction isolation techniques have proven successful, they suffer certain disadvantages in that they severely limit the surface area of the semiconductor body available for device fabrication. The reason for this limitation involves the fact that as the lateral isolation region diffuses into the semiconductor body in a direction perpendicular to the generally planar surface of the semiconductor wafer, it also spreads laterally in a direction parallel to the surface. Thus, the PN junction spreads towards the devices which are to be isolated. It is essential that the isolation junction not come in contact with the device to be isolated. Therefore, sufficient space must be provided between devices to account for this lateral spreading.
Another known technique for device isolation, termed the isoplanar technique involves the deposition of a silicon nitride film on the semiconductor surface, the etching of grooves through the film and into the semiconductor body, followed by thermal growth of silicon dioxide to fill the grooves. The silicon nitride film retards the growth of the oxide other than in the grooves. After the grooves are filled, the silicon nitride film is etched away to leave oxide isolated semiconductor islands with a planar surface.
A more desirable isolation technique which can be termed polyplanar is described in U.S. Pat. No. 3,979,237 issued Sept. 7, 1976, to Morcom et al. This technique which may combine the PN junction and isoplanar techniques uses dielectric isolation laterally and PN junction isolation on the bottom. According to the polyplanar isolation technique a thin film of protective material is deposited on the planar surface of a semiconductor wafer in which integrated circuits are to be fabricated. A mask conforming to the desired isolation pattern is provided over the exposed surface of the protective thin film and isolation grooves are etched through the film and into the semiconductor material. The grooves are of a sufficient depth to define the regions within which devices are to be fabricated. An insulator layer such as a film of silicon dioxide is then formed over the surfaces of the grooves. The remaining portions of the grooves are then filled with pyrolytically deposited dielectric material or other fill material capable of withstanding subsequent high temperature processing to the level of the original planar surface of the semiconductor body. Due to limitations in the manufacturing process, the film material will overfill the grooves and will coat surfaces other than the grooves themselves. The protective thin film functions to allow the excess film material to be removed from the surface of the semiconductor wafer without damaging the underlying planar surface of the semiconductor material. After removal of the excess film material, the thin film is removed by etching to expose a planar surface of isolated semiconductor islands. Conventional integrated circuit processing continues from this point. A full and complete description of this polyplanar isolation process is given in the aforementioned patent to Morcom et al and the reader is directed to that patent for a full understanding of this isolation process.